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(parent: 5ab4344) | patch
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
authorFelix Fietkau <[email protected]>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
committerFelix Fietkau <[email protected]>
Mon, 2 Nov 2015 18:20:51 +0000 (18:20 +0000)
commit5117f65475a651093db90a13f920c94f2875fceb
treeb2fb3f558930fc94dbe0c7b78bee2e58927e2cebtree | snapshot
parent5ab43440d83dc0a6795f6be64ebc78d06a2e92f2commit | diff
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.

Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <[email protected]>
Signed-off-by: Felix Fietkau <[email protected]>
SVN-Revision: 47363
target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch diff | blob | history
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